1. Field of the Invention
The present invention relates to metal oxide semiconductor field effect transistors (MOSFETs) and a method of making the same. More particularly, the present invention relates to MOSFETs having the construction wherein a gate is sandwiched between source and drains, and to a method of making the same.
2. Description of the Prior Art
Referring to FIG. 1, there is shown the construction of a conventional MOSFET. As shown in the drawing, the MOSFET comprises a p-type substrate 1 and a gate 3 having a gate oxide layer 2. The gate 3 has a high concentration n-type source region 4 and a high concentration n-type drain region 4a below its opposite edge portions r.sub.1, respectively.
In the construction shown in FIG. 1, a sharp high electric field is formed at both edge portions r.sub.1 of the gate 3 when a drive voltage is applied to the gate 3. As a result, hot electrons are generated at opposite edge portions r.sub.1 of the gate 3 and trapped in the gate oxide layer 2. The trapped electrons are re-combined with holes distributed in the boundary of the gate oxide layer 2. Consequently, the gate 3 can be driven only when the drive voltage exceeds a predetermined level. In fact, this MOSFET, as illustrated in FIG. 1, is in a disabled state. Thus, MOSFET of the construction of FIG. 1 has a problem of very low reliability.
In order to avoid the reduction of the life time and the reliability of MOSFETs, caused by the generation of hot electrons due to high electric fields formed at gate edges, there has been proposed a MOSFET of a lightly doped drain (LDD) construction shown in FIG. 2.
In the case of the LDD construction of a MOSFET, a gate oxide layer 6 and a gate 7 are formed in turn on a predetermined portion of a p-type substrate 5. On both sides of the gate oxide layer 6 and the gate 7, side wall oxide layers 8 are coated, respectively. A low concentration n-type source region 9 and a low concentration n-type drain region 9a are formed on the substrate 5 below side wall oxide layers 8, respectively. Below respective edge portions r.sub.3 of side wall oxide layer 8, a high concentration n-type source region 10 and a high concentration n-type drain region 10a are formed. That is, the gate 7 is provided at its opposite edge portions r.sub.2 with a low concentration n-type source region 9 and a low concentration n-type drain region 9a, so as to avoid the generation of hot electrons at the both edge portions r.sub.1. In this case, the material of the gate 7 is mainly polysilicon.
The operation of the MOSFET of the construction shown in FIG. 2 will now be described.
Typically, when a channel region is saturated as a high voltage is applied to gate and drain regions, a strong horizontal electric field extending from the drain region to the source region is generated at the region corresponding to the edge portion of the channel region.
In the MOSFET of the LDD construction of FIG. 2, however, the intensity of the horizontal electric field at edge portions r.sub.1 is attenuated due to the low concentration n-type drain 9a formed below the corresponding side wall oxide layer 8. As a result, the generation of ion impacts at the both edge portions r.sub.2 of the gate 7 is reduced, thereby desirably reducing the trapping of electrons in the gate oxide layer 6.
When a bias voltage is applied to gate 7, however, the electron concentration is greatly lowered at regions r.sub.2 of the low concentration n-type drain region 9a, as shown in FIG. 3. This is because a high potential difference occurs in the regions r.sub.2 by virtue of the fact that no bias from gate 7 is applied to the side wall oxide layers 8, thereby causing electrons to be concentrated toward the regions r.sub.2. Accordingly, many electrons are trapped in the side wall oxide layers 8, through the regions r.sub.2 and then re-combined with holes distributed in the boundary between the gate oxide layer 6 and the channel region, thereby increasing the actual bias voltage.
As a result, the manufactured element can not be driven by the bias voltage, which was predetermined in manufacturing the element, so that it becomes disabled. That is, the MOSFET of the construction of FIG. 2 has the disadvantages of a short life time and low reliability, since the peak of the horizontal electric field is not positioned at the region below the gate oxide layer 6 where it could be easily controlled, but at the region r.sub.2 below the side wall oxide layer 8.
In other words, the side wall oxide layer 8 is typically formed, for example by chemical vapor deposition (CVD), so that it has a degraded quality, over the gate oxide layer 6 which is formed by thermal oxidation. Over the gate oxide layer 6, therefore, the insulation characteristic of the side wall oxide layer 8 is degraded, thereby causing the electrons to be more easily trapped in the side wall oxide layer 8. This trapping of electrons in the side wall oxide layer 8 results in an undesirable variation of the resistance level of the drain, thereby causing the life time of the manufactured element to be shortened.
Although the disadvantages encountered in the prior art have been described in conjunction with P-type MOSFETs, n-type MOSFETs also encounter the same disadvantages.